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双游程编码的无关位填充算法 预览 被引量:6

The Algorithm of Filling X Bits in Dual-Run-Length Coding
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摘要 双游程编码是集成电路测试数据压缩的一种重要方法,可分为无关位填充和游程编码压缩两个步骤.现有文献大都着重在第二步,提出了各种不同的编码压缩算法,但是对于第一步的无关位填充算法都不够重视,损失了一定的潜在压缩率.本文首先分析了无关位填充对于测试数据压缩率的重要性,并提出了一种新颖的双游程编码的无关位填充算法,可以适用于不同的编码方法,从而得到更高的测试数据压缩率.该算法可以与多种双游程编码算法结合使用,对解码器的硬件结构和芯片实现流程没有任何的影响.在ISCAS89的基准电路的实验表明,对于主流的双游程编码算法,结合该无关位填充算法后能提高了6%-9%的测试数据压缩率. The dual-run-length codes are the important technique for test data compression. Test compression has two steps: first,the don' t-care bits in the test data are filled with 0 or 1s and the test data are divided into rtm sequences;second,every run in the sequences is converted to the compression code according to the given encoding algorithm. However, all the former existing papers focus on the second step, ignoring the importance of the first step thus to lose a certain potential compression ratio. In this paper, we address the importance of don' t-care bits filling to test data compression ratio and propose a novel algorithm, which fills don' t-care bits according to the selecting codes to achieve the higher compression ratio. This algorithm can be used with many dualrun-length codes without impacting on the decoder structure or the chip implementation flow. For the mainstream dual-run-length codes,the compression ratio is improved by 6%-9%.
作者 方昊 姚博 宋晓笛 程旭 FANG Hao, YAO Bo, SONG Xiao-di, CHENG Xu (Room 1815, Science Building 1, Peking University, Beijing 100871, China)
机构地区 北京大学理科
出处 《电子学报》 EI CAS CSCD 北大核心 2009年第1期 1-6,共6页 Acta Electronica Sinica
基金 国家863高技术研究发展计划(No.2006AA010202)
关键词 集成电路测试 测试数据压缩 游程编码 无关位填充 IC test test data compression run-length codes fill don' t-care bits
作者简介 方昊 男,1981年出生于浙江杭州,北京大学计算机系博士研究生,研究方向为数字电路的可测性设计、时序优化和分析、时钟树调度和生成.E-mail:fanghao@mprc.pku.edu.cn 姚博 男,1983年出生于河南南阳,北京大学计算机系硕士研究生,研究方向为数字电路的可测性设计.E—mail:syaobo@mprc.pku.edu.cn 宋晓笛 男,1979年出生于北京,英国爱丁堡大学硕士,长期从事数字信号处理算法及相关超大规模集成电路设计研究.曾任“十五”八六三项目课题负责人,并参与过其他多项国家八六三项目.主要研究方向为软硬件协同设计、数字信号处理和多核系统芯片.E—mail:songxiaodi@pku.edu.cn 程旭 男,1967年出生于湖北襄樊,教授,博士生导师.北京大学微处理器研究开发中心主任、计算机科学技术系主任、计算机系统结构研究所所长、国家“十五”八六三计划超大规模集成电路设计专项专家组成员、中国通信学会专用集成电路委员会副主任委员.主要研究方向为高性能微处理器、系统芯片、嵌入式系统、指令级并行、优化编译、软硬件协同设计等.E-mail:chengxu@mprc.pku.edu.cn
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