为了提高基于SRAM的FPGA（SFPGA）上的容软错误能力,提出了一种基于软错误率（soft error rate,SER）评估的装箱算法SER-Tvpack.通过结合软错误率的两个组成部分错误传播率（error propagation probability,EPP）和节点错误率（node error rate,NER）,得到软错误评估标准SER的估算值,并将该值作为可靠性因子加入到代价函数中指导装箱过程,以减少装箱后可编程逻辑块（configuration logic block,CLB）之间互连的软错误率,从而提高设计的可靠性.对20个MCNC基准电路（最大基准电路集）进行实验,结果表明,与基准时序装箱算法T-Vpack及已有的容错装箱算法FTvpack相比较,软故障率分别减少了14.5%和4.11%.而且,与F-Tvpack比较,在仅增加0.04%的面积开销下,减少了2.31%的关键路径的时延,提供了较好的时序性能.
With the widely use of SRAM-based FPGA （SFPGA） in various fields, reliability becomes increasingly an important concern in SFPGAs. We propose an SER （soft error rate） estimation-based clustering method, namely SER-Tvpack, by adding SER as a reliability factor to the cost function. Combining EPP （error propagation probability） and estimated NER （node error rate） by using the existing ISPL metric, which has been shown to predict every post-placement wirelength accurately, we can estimate the NER factor and get the estimated SER in the clustering stage. According to the fact that the SER of inter-CLBs nets is much higher than that inside CLBs, SER-Tvpack reduces the soft fault rate （SFR） by the means of absorbing high SER nets into the CLBs as much as possible and leaving the low SER nets out of the CLBs. Experimental results show that the proposed SER-Tvpack reduces SFR by 14.5% compared with the baseline T-Vpack, while the previous F-Tvpack reduces SFR by 4.11%. Furthermore, it achieves better performance for reducing the critical path delay by 2.31% in comparison with F-Tvpack, with only 0.04% area overhead increase.
Journal of Computer Research and Development
soft error rate （SER）
single event upset （SEU）
Xia Jing, born in 1988. Master at the College of Information Science and Engineering, Hunan University. Her main research interests include VLSI test and verification, design against soft error.xiajing@ict. ac. cn
Wang Tiancheng, born in 1983. Received his master degree from the Institute of Computing Technology, Chinese Academy of Sciences in 2009. Engineer at the State Key Laboratory of Computer Architecture.His main research interests include VLSI design and verification.
Lu Tao, born in 1978. Associate professor at the State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences. Member of China Computer Federation. Her main research interests include VLSI/SOC design, test and verification.
LiHuawei, born in 1974. Professor at the State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences. Senior member of IEEE and China Computer Federation. Her main research interests include VLSI test, verification and reliability design.
Kuang Jishun, born in 1959. Professor at the College of Information Science and Engineering, Hunan University. Senior member of China Computer Federation. His main research interests include IC test and embedded system.通信作者：邝继顺（jshkuang@hotmail．com）